Sciweavers

46 search results - page 2 / 10
» A high performance bus communication architecture through bu...
Sort
View
DATE
2003
IEEE
98views Hardware» more  DATE 2003»
13 years 10 months ago
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
System-on-chip (SoC) designs use bus protocols for high performance data transfer among the Intellectual Property (IP) cores. These protocols incorporate advanced features such as...
Abhik Roychoudhury, Tulika Mitra, S. R. Karri
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
14 years 5 months ago
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks
The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Bo...
Thomas D. Richardson, Chrysostomos Nicopoulos, Don...
FTCS
1998
77views more  FTCS 1998»
13 years 6 months ago
Strong Partitioning Protocol for a Multiprocessor VME System
The trend in implementing today's embedded applications is toward the use of commercial-off-the-shelf open architecture. Reducing costs and facilitating systems integration a...
Mohamed F. Younis, Jeffrey X. Zhou, Mohamed Abouta...
DAC
2008
ACM
14 years 6 months ago
Latency and bandwidth efficient communication through system customization for embedded multiprocessors
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
Chenjie Yu, Peter Petrov
ASPDAC
2008
ACM
94views Hardware» more  ASPDAC 2008»
13 years 7 months ago
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architec...
Sujan Pandey, Rolf Drechsler