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ICCAD
2005
IEEE
176views Hardware» more  ICCAD 2005»
14 years 2 months ago
Statistical gate sizing for timing yield optimization
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
BMCBI
2008
184views more  BMCBI 2008»
13 years 4 months ago
"TOF2H": A precision toolbox for rapid, high density/high coverage hydrogen-deuterium exchange mass spectrometry via an LC-MALDI
Background: Protein-amide proton hydrogen-deuterium exchange (HDX) is used to investigate protein conformation, conformational changes and surface binding sites for other molecule...
Pornpat Nikamanon, Elroy Pun, Wayne Chou, Marek D....
APLAS
2009
ACM
13 years 11 months ago
Large Spurious Cycle in Global Static Analyses and Its Algorithmic Mitigation
We present a simple algorithmic extension of the classical call-strings approach to mitigate substantial performance degradation caused by spurious interprocedural cycles. Spuriou...
Hakjoo Oh
SLIP
2009
ACM
13 years 11 months ago
Closed-form solution for timing analysis of process variations on SWCNT interconnect
In this paper, a comprehensive and fast method is presented for the timing analysis of process variations on single-walled carbon nanotube (SWCNT) bundles. Unlike previous works t...
Peng Sun, Rong Luo
DAC
2008
ACM
14 years 6 months ago
A framework for block-based timing sensitivity analysis
Since process and environmental variations can no longer be ignored in high-performance microprocessor designs, it is necessary to develop techniques for computing the sensitiviti...
Sanjay V. Kumar, Chandramouli V. Kashyap, Sachin S...