444 search results - page 2 / 89 » A low power high performance switched-current multiplier |
DAC
1999
ACM
14 years 6 months ago
1999
ACM
We present a novel approach that minimizes the power consumption of embedded core-based systems through hardware/software partitioning. Our approach is based on the idea of mapping...
CDES
2006
13 years 6 months ago
2006
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
ARITH
2003
IEEE
13 years 10 months ago
2003
IEEE
We propose a split array multiplier organized in a left-to-right leapfrog (LRLF) structure with reduced delay compared to conventional array multipliers. Moreover, the proposed de...
TVLSI
2010
13 years 17 hour ago
2010
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...
EWSN
2012
Springer
12 years 1 months ago
2012
Springer
Abstract. Some have argued that the dichotomy between high-performance operation and low resource utilization is false – an artifact that will soon succumb to Moore’s Law and c...