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DATE
2007
IEEE
150views Hardware» more  DATE 2007»
9 years 8 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
ISCAS
2008
IEEE
133views Hardware» more  ISCAS 2008»
9 years 8 months ago
A hybrid self-testing methodology of processor cores
—Software-based self-test (SBST) is a promising new technology for at-speed testing of embedded processors in SoC systems. This paper introduces an effective and efficient new ho...
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
CODES
2005
IEEE
9 years 7 months ago
Future processors: flexible and modular
The ability to continue increasing processor frequency and single thread performance is being severely limited by exponential increases in leakage and active power. To continue to...
Charlie Johnson, Jeff Welser
MICRO
2010
IEEE
173views Hardware» more  MICRO 2010»
8 years 11 months ago
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...
Eric S. Chung, Peter A. Milder, James C. Hoe, Ken ...
DATE
2003
IEEE
104views Hardware» more  DATE 2003»
9 years 6 months ago
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...
George Lykakis, N. Mouratidis, Kyriakos Vlachos, N...
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