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» A low-power VLSI architecture for turbo decoding
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TVLSI
2002
100views more  TVLSI 2002»
13 years 5 months ago
Architectural strategies for low-power VLSI turbo decoders
Abstract--The use of "turbo codes" has been proposed for several applications, including the development of wireless systems, where highly reliable transmission is requir...
Guido Masera, M. Mazza, Gianluca Piccinini, F. Vig...
VLSID
2003
IEEE
108views VLSI» more  VLSID 2003»
14 years 5 months ago
A Low Power-Delay Product Page-Based Address Bus Coding Method
The working-zone encoding (WZE) method employing locality of memory reference was previously proposed to reduce address bus switching activity. This paper presents an encoding met...
Chi-Ming Tsai, Guang-Wan Liao, Rung-Bin Lin
ICCAD
2000
IEEE
148views Hardware» more  ICCAD 2000»
13 years 9 months ago
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is proposed t...
Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, ...
ISVLSI
2005
IEEE
115views VLSI» more  ISVLSI 2005»
13 years 11 months ago
High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization
The authors present a turbo soft-in soft-out (SISO) decoder based on Max-Log maximum a posteriori (ML-MAP) algorithm implemented with sliding window (SW) method. A novel technique...
J. H. Han, Ahmet T. Erdogan, Tughrul Arslan