45 search results - page 8 / 9 » A low-power clock frequency multiplier |
DAC
2004
ACM
14 years 7 months ago
2004
ACM
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
VLSID
2005
IEEE
14 years 6 months ago
2005
IEEE
Two Simple structures of low-power Dual-edge triggered Static Pulsed Flip-Flops (DSPFF) are presented in this paper. They are composed of a dualedge pulse generator and a static f...
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
Dynamic voltage scaling (DVS) is a technique that varies the supply voltage and clock frequency based on the computation load to provide desired performance with the minimal amoun...
DATE
2008
IEEE
14 years 16 days ago
2008
IEEE
The Software-Defined Radio (SDR) concept aims to enabling costeffective multi-mode baseband solutions for wireless terminals. However, the growing complexity of new communication ...
MICRO
2002
IEEE
13 years 11 months ago
2002
IEEE
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...