Sciweavers

14 search results - page 3 / 3
» A method of redundant clocking detection and power reduction...
Sort
View
HPCA
2005
IEEE
13 years 11 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
ADHOC
2008
103views more  ADHOC 2008»
13 years 5 months ago
Impact of sensor-enhanced mobility prediction on the design of energy-efficient localization
Energy efficiency and positional accuracy are often contradictive goals. We propose to decrease power consumption without sacrificing significant accuracy by developing an energy-...
Chuang-Wen You, Polly Huang, Hao-Hua Chu, Yi-Chao ...
ISCA
2006
IEEE
169views Hardware» more  ISCA 2006»
13 years 11 months ago
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
Chuanjun Zhang
CASES
2006
ACM
13 years 9 months ago
Cost-efficient soft error protection for embedded microprocessors
Device scaling trends dramatically increase the susceptibility of microprocessors to soft errors. Further, mounting demand for embedded microprocessors in a wide array of safety c...
Jason A. Blome, Shantanu Gupta, Shuguang Feng, Sco...