CASES 2006 - PDF Preprint Papers

CASES 2006 International Conference on Compilers

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CASES
2006
ACM

227views System Software» more CASES 2006»

Automatic performance model construction for the fast software exploration of new hardware designs

13 years 10 months ago

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Developing an optimizing compiler for a newly proposed architecture is extremely difﬁcult when there is only a simulator of the machine available. Designing such a compiler requ...

John Cavazos, Christophe Dubach, Felix V. Agakov, ...

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Id	Views	Title	Status

1	227	Automatic performance model construction for the fast software exploration of new hardware designs	claim
2	216	Probabilistic arithmetic and energy efficient embedded signal processing	claim
3	203	Adaptive object code compression	claim
4	196	A dynamic code placement technique for scratchpad memory using postpass optimization	claim
5	187	Limitations of special-purpose instructions for similarity measurements in media SIMD extensions	claim
6	186	CFLRU: a replacement algorithm for flash memory	claim
7	185	Reducing energy of virtual cache synonym lookup using bloom filters	claim
8	177	A case study of multi-threading in the embedded space	claim
9	173	Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations	claim
10	166	Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP	claim
11	164	Improving the performance and power efficiency of shared helpers in CMPs	claim
12	161	FlashCache: a NAND flash memory file cache for low power web servers	claim
13	157	Integrated scratchpad memory optimization and task scheduling for MPSoC architectures	claim
14	154	Cost-efficient soft error protection for embedded microprocessors	claim
15	146	Adapting compilation techniques to enhance the packing of instructions into registers	claim
16	144	Automated compile-time and run-time techniques to increase usable memory in MMU-less embedded systems	claim
17	142	Adaptive and flexible dictionary code compression for embedded applications	claim
18	142	A dynamic binary instrumentation engine for the ARM architecture	claim
19	141	Methods for power optimization in distributed embedded systems with real-time requirements	claim
20	139	High-performance packet classification algorithm for many-core and multithreaded network processor	claim
21	137	Memory optimization by counting points in integer transformations of parametric polytopes	claim
22	135	Supporting precise garbage collection in Java Bytecode-to-C ahead-of-time compiler for embedded systems	claim
23	132	Compiler optimization of embedded applications for an adaptive SoC architecture	claim
24	127	Scalable subgraph mapping for acyclic computation accelerators	claim
25	117	Efficient architectures through application clustering and architectural heterogeneity	claim
26	116	Incremental elaboration for run-time reconfigurable hardware designs	claim
27	111	Code transformation strategies for extensible embedded processors	claim
28	109	High-level power analysis for multi-core chips	claim
29	109	An accurate and efficient simulation-based analysis for worst case interruption delay	claim
30	103	Extensible control architectures	claim
31	103	State space reconfigurability: an implementation architecture for self modifying finite automata	claim
32	99	Mitigating soft error failures for multimedia applications by selective data protection	claim
33	98	Modeling heterogeneous SoCs with SystemC: a digital/MEMS case study	claim
34	95	High-level languages for small devices: a case study	claim
35	88	Minimizing bank selection instructions for partitioned memory architecture	claim
36	87	A network agent for diagnosis and analysis of real-time Ethernet networks	claim
37	80	Power efficient branch prediction through early identification of branch addresses	claim
38	78	Protected heap sharing for memory-constrained java environments	claim
39	75	Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures	claim
40	69	Syntax-driven implementation of software programming language control constructs and expressions on FPGAs	claim

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