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DATE
2006
IEEE
109views Hardware» more  DATE 2006»
13 years 10 months ago
A methodology for mapping multiple use-cases onto networks on chips
A communication-centric design approach, Networks on Chips (NoCs), has emerged as the design paradigm for designing a scalable communication infrastructure for future Systems on C...
Srinivasan Murali, Martijn Coenen, Andrei Radulesc...
ISCAS
2007
IEEE
104views Hardware» more  ISCAS 2007»
13 years 11 months ago
Evaluation of Algorithms for Low Energy Mapping onto NoCs
—Systems on Chip (SoCs) congregate multiple modules and advanced interconnection schemes, such as networks on chip (NoCs). One relevant problem in SoC design is module mapping on...
César A. M. Marcon, Edson I. Moreno, Ney La...
DATE
2004
IEEE
158views Hardware» more  DATE 2004»
13 years 8 months ago
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the e...
Srinivasan Murali, Giovanni De Micheli
DSD
2006
IEEE
95views Hardware» more  DSD 2006»
13 years 8 months ago
Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication
We present a performance-oriented refinement approach that refines a perfectly synchronous communication model onto Network-on-Chip (NoC) communication. We first identify four bas...
Zhonghai Lu, Ingo Sander, Axel Jantsch
ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
13 years 9 months ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...