Sciweavers

6 search results - page 1 / 2
» A methodology for the design of AHB bus master wrappers
Sort
View
DSD
2003
IEEE
109views Hardware» more  DSD 2003»
13 years 10 months ago
A methodology for the design of AHB bus master wrappers
This paper proposes a methodology and a basic structure for the design of wrappers used to adapt cores for use as bus masters. The AMBA AHB protocol is used as a case study in thi...
Marc Bertola, Guy Bois
DATE
2003
IEEE
108views Hardware» more  DATE 2003»
13 years 10 months ago
System-Level Power Analysis Methodology Applied to the AMBA AHB Bus
The specification on power consumption of a digital system is extremely important due to the growing relevance of the market of portable devices and must be taken into account sin...
Marco Caldari, Massimo Conti, Massimo Coppola, Pao...
ISQED
2006
IEEE
118views Hardware» more  ISQED 2006»
13 years 10 months ago
Language-Based High Level Transaction Extraction on On-chip Buses
Abstract— With the increasing in silicon densities, SoC designs are the stream in modern electronics systems. Accordingly, the verification for SoC designs is crucial. One of th...
Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chie...
TECS
2008
122views more  TECS 2008»
13 years 4 months ago
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
Gunar Schirner, Rainer Dömer
CODES
2003
IEEE
13 years 10 months ago
Security wrappers and power analysis for SoC technologies
Future wireless internet enabled devices will be increasingly powerful supporting many more applications including one of the most crucial, security. Although SoCs offer more resi...
Catherine H. Gebotys, Y. Zhang