28 search results - page 2 / 6 » A multi-level static memory cell |
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper introduces a static multi-level memory cell that was conceived to store state variables in neuromorphic onchip learning applications. It consists of a capacitance that ...
CAL
2002
13 years 5 months ago
2002
Abstract-This paper proposes the use of four-transistor (4T) cache and branch predictor array cell designs to address increasing worries regarding leakage power dissipation. While ...
VLSID
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper, for the first time, we analyze non-quasistatic (NQS) effects during single-event upsets (SEUs) in deep-submicron (DSM) MOS devices, using extensive 2D device, BSIM...
ICCD
2001
IEEE
14 years 2 months ago
2001
IEEE
Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption ...
VLSID
2009
IEEE
14 years 5 months ago
2009
IEEE
Abstract-- Single-ended static random access memory (SESRAM) is well known for their tremendous potential of low active power and leakage dissipations. In this paper, we present a ...