75 search results - page 1 / 15 » A multiple clocking scheme for low power RTL design |
ISLPED
1995
ACM
13 years 8 months ago
1995
ACM
This paper presents an e ective multiple clocking scheme for lower power RTL circuit design. The basis is to partition a behavioral description of the circuit into m modules fed b...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
ISLPED
2000
ACM
13 years 8 months ago
2000
ACM
This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. Th...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
DAC
1998
ACM
13 years 9 months ago
1998
ACM
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...