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» A new heuristic algorithm for reversible logic synthesis
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OSDI
1994
ACM
13 years 6 months ago
Scheduling for Reduced CPU Energy
The energy usage of computer systems is becoming more important, especially for battery operated systems. Displays, disks, and cpus, in that order, use the most energy. Reducing t...
Mark Weiser, Brent B. Welch, Alan J. Demers, Scott...
ML
2002
ACM
123views Machine Learning» more  ML 2002»
13 years 4 months ago
Feature Generation Using General Constructor Functions
Most classification algorithms receive as input a set of attributes of the classified objects. In many cases, however, the supplied set of attributes is not sufficient for creatin...
Shaul Markovitch, Dan Rosenstein
JIIS
2008
89views more  JIIS 2008»
13 years 5 months ago
A note on phase transitions and computational pitfalls of learning from sequences
An ever greater range of applications call for learning from sequences. Grammar induction is one prominent tool for sequence learning, it is therefore important to know its proper...
Antoine Cornuéjols, Michèle Sebag
FPGA
2007
ACM
163views FPGA» more  FPGA 2007»
13 years 11 months ago
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based ...
Jason Cong, Kirill Minkovich
ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
13 years 3 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen