17 search results - page 1 / 4 » A new look at the conditions for the synthesis of speed-inde... |
GLVLSI
1995
IEEE
13 years 8 months ago
1995
IEEE
GLVLSI
2010
IEEE
13 years 10 months ago
2010
IEEE
Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising directio...
AAAI
1997
13 years 6 months ago
1997
We report on the performance of an enhanced version of the “Davis-Putnam” (DP) proof procedure for propositional satisfiability (SAT) on large instances derived from realworld...
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance of the interconnect delay in deepsubmicron technologies. We first show that conv...
ISPD
2000
ACM
13 years 9 months ago
2000
ACM
In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such ...