8 search results - page 1 / 2 » A novel flash analog-to-digital converter |
ISCAS
2008
IEEE
14 years 12 days ago
2008
IEEE
—In this paper a new ADC architecture of flash type is proposed. This proposed N-bit flash ADC replaces the (2N -1)-toN encoder with two (2N/2 -1)-to-(N/2) encoders to accomplish...
ISCAS
1999
IEEE
13 years 10 months ago
1999
IEEE
ISMVL
2000
IEEE
13 years 10 months ago
2000
IEEE
We present a novel multiple-threshold circuit using resonant-tunneling diodes (RTDs). The logic operation is based on detecting a switching sequence in the RTD circuit. This schem...
ISLPED
2004
ACM
13 years 11 months ago
2004
ACM
In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-process...
ISCAS
1994
IEEE
13 years 10 months ago
1994
IEEE
A novel self-trimming algorithm for A/D converters [1,2] has been presented which continually trims thresholds in the flash A/D subconverters of two-stage and pipelined A/D conver...