287 search results - page 3 / 58 » A novel improvement technique for high-level test synthesis |
ISSS
2002
IEEE
13 years 9 months ago
2002
IEEE
We introduce a new approach, “Dynamic Common Sub-expression Elimination (CSE)”, that dynamically eliminates common sub- expressions based on new opportunities created during s...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Loop unrolling is a well-known compiler optimization that can lead to significant performance improvements. When used in High Level Synthesis (HLS) unrolling can affect the contr...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...
ASAP
2007
IEEE
13 years 6 months ago
2007
IEEE
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
TRETS
2010
13 years 3 months ago
2010
s, and abstractions, typically enabling faster development times than with traditional Hardware ion Languages (HDLs). However, programming at a higher level of abstraction is typic...