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FCCM
2004
IEEE
269views VLSI» more  FCCM 2004»
13 years 9 months ago
FPGA Based Network Intrusion Detection using Content Addressable Memories
In this paper, we introduce a novel architecture for a hardware based network intrusion detection system (NIDS). Current software-based NIDS are too compute intensive and can not ...
Long Bu, John A. Chandy
AHS
2006
IEEE
145views Hardware» more  AHS 2006»
13 years 9 months ago
The Gannet Service-Based SoC: A Service-level Reconfigurable Architecture
We propose a novel type of dynamically reconfigurable System-on-Chip architecture, the Gannet service-based architecture. This novel concept addresses the issue of systemlevel rec...
Wim Vanderbauwhede
ANCS
2009
ACM
13 years 3 months ago
A NFA-based programmable regular expression match engine
Pattern matching is the most computation intensive task of a network intrusion detection system (NIDS). In this paper we present a hardware architecture to speed up the pattern mat...
Derek Pao
MICRO
2003
IEEE
128views Hardware» more  MICRO 2003»
13 years 11 months ago
IPStash: a Power-Efficient Memory Architecture for IP-lookup
Abstract—High-speed routers often use commodity, fully-associative, TCAMs (Ternary Content Addressable Memories) to perform packet classification and routing (IP lookup). We prop...
Stefanos Kaxiras, Georgios Keramidas
JVCIR
2008
92views more  JVCIR 2008»
13 years 5 months ago
Hardware implementation of a disparity estimation scheme for real-time compression in 3D imaging applications
This paper presents a novel hardware implementation of a disparity estimation scheme targeted to real-time Integral Photography (IP) image and video sequence compression. The soft...
Dionisis Chaikalis, Nikos Sgouros, Dimitris Maroul...