17 search results - page 2 / 4 » A parallel IEEE P754 decimal floating-point multiplier |
ARITH
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper we propose an architecture for the computation of the double—precision floating—point multiply—add fused (MAF) operation A + (B × C) that permits to compute ...
CDES
2006
13 years 7 months ago
2006
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
ARVLSI
1995
IEEE
13 years 9 months ago
1995
IEEE
This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural mod...
ICCD
2007
IEEE
14 years 2 months ago
2007
IEEE
Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it are included in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P75...
FPL
2006
Springer
13 years 9 months ago
2006
Springer
FPGAs have reached densities that can implement floatingpoint applications, but floating-point operations still require a large amount of FPGA resources. One major component of IE...