44 search results - page 3 / 9 » A reuse scenario for the VHDL-based hardware design flow |
DT
2006
13 years 5 months ago
2006
the abstraction level at which designers express systems, enabling new levels of design reuse, and providing for design chain integration ool flows and abstraction levels. The purp...
ICCD
2005
IEEE
14 years 2 months ago
2005
IEEE
The implementation of interconnect is becoming a significant challenge in modern IC design. Both synchronous and asynchronous strategies have been suggested to manage this problem...
ESORICS
2006
Springer
13 years 9 months ago
2006
Springer
Abstract. While processor based systems often enforce memory protection to prevent the unintended sharing of data between processes, current systems built around reconfigurable har...
COMPSEC
2008
13 years 5 months ago
2008
While general-purpose processor based systems are built to enforce memory protection to prevent the unintended sharing of data between processes, current systems built around reco...
GLVLSI
2010
IEEE
13 years 7 months ago
2010
IEEE
Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code in a more energy efficient structure than the level ...