30 search results - page 6 / 6 » A routing approach to reduce glitches in low power FPGAs |
DSD
2007
IEEE
13 years 11 months ago
2007
IEEE
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
NOCS
2010
IEEE
13 years 3 months ago
2010
IEEE
Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing po...
CLEANDB
2006
ACM
13 years 11 months ago
2006
ACM
Outliers are very common in the environmental data monitored by a sensor network consisting of many inexpensive, low fidelity, and frequently failed sensors. The limited battery ...
MICRO
2009
IEEE
14 years 3 days ago
2009
IEEE
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
DATE
2008
IEEE
13 years 12 months ago
2008
IEEE
—Governmental Transportation Authorities' interest in Car to Car and Car to Infrastructure has grown dramatically over the last few years in order to increase the road safet...