9 search results - page 2 / 2 » A scalable and programmable architecture for 2-D DWT decodin... |
ICIP
2004
IEEE
14 years 6 months ago
2004
IEEE
The recent advances in non-scalable video encoding brought by the H.264/AVC standard offered significant improvements in terms of rate-distortion performance. This paper proposes ...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
VLSISP
2008
13 years 4 months ago
2008
Abstract-- This paper presents the architecture of an Asynchronous Array of simple Processors (AsAP), and evaluates its key architectural features as well as its performance and en...
VLSISP
2008
13 years 4 months ago
2008
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...