5 search results - page 1 / 1 » A scalable micro wireless interconnect structure for CMPs |
MOBICOM
2009
ACM
13 years 11 months ago
2009
ACM
This paper describes an unconventional way to apply wireless networking in emerging technologies. It makes the case for using a two-tier hybrid wireless/wired architecture to inte...
CDES
2008
13 years 6 months ago
2008
Although directory-based cache coherence protocols are the best choice when designing chip multiprocessor architectures (CMPs) with tens of processor cores on chip, the memory ove...
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
HIPEAC
2011
Springer
12 years 4 months ago
2011
Springer
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...