132 search results - page 2 / 27 » A statistical multiprocessor cache model |
IEEEPACT
2009
IEEE
13 years 3 months ago
2009
IEEE
Resource sharing can cause unfair and unpredictable performance of concurrently executing applications in Chip-Multiprocessors (CMP). The shared last-level cache is one of the mos...
AINA
2009
IEEE
14 years 5 days ago
2009
IEEE
This paper presents a modeling method particularly suited to analyze interactions between Message Passing Interface MPI library execution and distributed cache coherence protocol....
TC
1998
13 years 5 months ago
1998
—This paper describes the methods used to formulate and validate the memory subsystem of the cache-coherent Sun Scalable emory MultiProcessor (S3.mp) at three levels of abstracti...
SIGMETRICS
1996
ACM
13 years 9 months ago
1996
ACM
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
ISCA
1996
IEEE
13 years 9 months ago
1996
IEEE
In the future, advanced integrated circuit processing and packaging technology will allow for several design options for multiprocessor microprocessors. In this paper we consider ...