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FPGA
1999
ACM
142views FPGA» more  FPGA 1999»
13 years 10 months ago
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems
Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we addr...
Abdel Ejnioui, N. Ranganathan
ICCD
2007
IEEE
132views Hardware» more  ICCD 2007»
14 years 3 months ago
A position-insensitive finished store buffer
This paper presents the Finished Store Buffer (or FSB), an alternative and position-insensitive approach for building a scalable store buffer for an out-of-order processor. Exploi...
Erika Gunadi, Mikko H. Lipasti
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
13 years 10 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
CGF
2006
173views more  CGF 2006»
13 years 6 months ago
C-BDAM - Compressed Batched Dynamic Adaptive Meshes for Terrain Rendering
We describe a compressed multiresolution representation for supporting interactive rendering of very large planar and spherical terrain surfaces. The technique, called Compressed ...
Enrico Gobbetti, Fabio Marton, Paolo Cignoni, Marc...
ICCAD
2004
IEEE
128views Hardware» more  ICCAD 2004»
14 years 3 months ago
Power estimation for cycle-accurate functional descriptions of hardware
— Cycle-accurate functional descriptions (CAFDs) are being widely adopted in integrated circuit (IC) design flows. Power estimation can potentially benefit from the inherent in...
Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj...