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FPGA
2001
ACM

A pipelined architecture for partitioned DWT based lossy image compression using FPGA's

12 years 6 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in literature assume random access to the whole image. This makes the algorithms unsuitable for hardware solutions because of extensive access to external memory. Here, we present an efficient architecture for computing DWT of images, which is based on a partitioned approach for lossy image compression [3]. The architecture achieves its computational power by using pipelining and taking advantage of the flexible memory configurations available in FPGA’s. Categories and Subject Descriptors I.4.2 [Image Processing and Computer Vision]: Compression (Coding)—Approximate methods; B.2.1 [Arithmetic and Logic Structures]: Design Styles—pipelining; B.7.1 [Integrated Circuits]: Types and Design Styles—Algorithms implemented in hardware General Terms Design, Performance, Algorithm Keywords pipelining, wavelet tr...
Jörg Ritter, Paul Molitor
Added 28 Jul 2010
Updated 28 Jul 2010
Type Conference
Year 2001
Where FPGA
Authors Jörg Ritter, Paul Molitor
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