88 search results - page 1 / 18 » A succinct memory model for automated design debugging |
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
— In today’s complex SoC designs, verification and debugging are becoming ever more crucial and increasingly timeconsuming tasks. The prevalence of embedded memories adds to t...
FMCAD
2009
Springer
13 years 11 months ago
2009
Springer
—Given an erroneous design, functional verification returns an error trace exhibiting a mismatch between the specification and the implementation of a design. Automated design ...
FASE
2001
Springer
13 years 9 months ago
2001
Springer
This paper describes the design and implementation of a tool for C programs that provides run-time checks based on type information. The tool instruments a program to monitor the t...
DAC
2002
ACM
14 years 5 months ago
2002
ACM
One of the main goals of coverage tools is to provide the user with informative presentation of coverage information. Specifically, information on large, cohesive sets of uncovere...
VLSID
2008
IEEE
14 years 5 months ago
2008
IEEE
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...