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IEEEPACT
2006
IEEE
13 years 11 months ago
Core architecture optimization for heterogeneous chip multiprocessors
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi
CODES
1999
IEEE
13 years 10 months ago
An MPEG-2 decoder case study as a driver for a system level design methodology
We present a case study on the design of a heterogeneous architecture for MPEG-2 video decoding. The primary objective of the case study is the validation of the SPADE methodology...
Pieter van der Wolf, Paul Lieverse, Mudit Goel, Da...
DSD
2008
IEEE
124views Hardware» more  DSD 2008»
14 years 7 days ago
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level
This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systems on-Chip (MPSoC), called GRAPES. The approach features flexibilit...
Matteo Monchiero, Gianluca Palermo, Cristina Silva...
ECBS
2005
IEEE
93views Hardware» more  ECBS 2005»
13 years 11 months ago
Embedded System Engineering Using C/C++ Based Design Methodologies
This paper analyzes and compares the effectiveness of various system level design methodologies in assessing performance of embedded computing systems from the earliest stages of ...
Claudio Talarico, Aseem Gupta, Ebenezer Peter, Jer...
DATE
2010
IEEE
121views Hardware» more  DATE 2010»
13 years 11 months ago
Cost modeling and cycle-accurate co-simulation of heterogeneous multiprocessor systems
—In this paper, we present a method to analyze different implementations of stream-based applications on heterogeneous multiprocessor systems. We take both resource usage and per...
Sven van Haastregt, Eyal Halm, Bart Kienhuis