19 search results - page 2 / 4 » A timing-constrained simultaneous global routing algorithm |
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
In this paper, we propose a new methodology to integrate circuit transformation into routing. More specifically, this paper shows an approach for performing routing and wire recon...
FPGA
2005
ACM
13 years 10 months ago
2005
ACM
Logic duplication is an effective method for improving circuit performance. In this paper we present an algorithm named SPD that performs simultaneous placement and duplication to...
DAC
2002
ACM
14 years 5 months ago
2002
ACM
Conventional global routing minimizes total wire length and congestion. Experiments using large industrial benchmark circuits show that up to 24% of nets in such routing solutions...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
-- Timing optimization is an important goal of global routing in deep submicron era. To guarantee the timing performance of the circuit, merely adopting topology optimization becom...
FPGA
2003
ACM
13 years 10 months ago
2003
ACM
The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently dev...