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ISCAS
1999
IEEE
61views Hardware» more  ISCAS 1999»
13 years 9 months ago
A transformation for computational latency reduction in turbo-MAP decoding
The SOVA and the log-MAP are commonly used in turbo decoding. In this paper, we propose to modify the sliding window MAP-algorithm in [5]to reduce the computational delay even fur...
Arun Raghupathy, K. J. Ray Liu
ICML
2006
IEEE
14 years 5 months ago
Online decoding of Markov models under latency constraints
The Viterbi algorithm is an efficient and optimal method for decoding linear-chain Markov Models. However, the entire input sequence must be observed before the labels for any tim...
Mukund Narasimhan, Paul A. Viola, Michael Shilman
VLSID
2006
IEEE
158views VLSI» more  VLSID 2006»
13 years 11 months ago
Programmable LDPC Decoder Based on the Bubble-Sort Algorithm
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
DAC
2009
ACM
13 years 8 months ago
Reduction techniques for synchronous dataflow graphs
The Synchronous Dataflow (SDF) model of computation is popular for modelling the timing behaviour of real-time embedded hardware and software systems and applications. It is an es...
Marc Geilen
DAC
2008
ACM
14 years 6 months ago
Latency and bandwidth efficient communication through system customization for embedded multiprocessors
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
Chenjie Yu, Peter Petrov