8 search results - page 1 / 2 » A unified methodology for power supply noise reduction in mo... |
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
In this paper, we present a novel design methodology to combat the ever-aggravating high frequency power supply noise (di/dt) in modern microprocessors. Our methodology integrates ...
ISCA
2003
IEEE
13 years 10 months ago
2003
IEEE
Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause ...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
This paper proposes Noise-Direct, a design methodology for power integrity aware floorplanning, using microarchitectural feedback to guide module placement. Stringent power constr...
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
As technology scales down, power supply noise is becoming a performance and reliability bottleneck in modern VLSI. We propose a power supply noise-aware design methodology for hig...
HPCA
2002
IEEE
14 years 5 months ago
2002
IEEE
As the power consumption of modern highperformance microprocessors increases beyond 100W, power becomes an increasingly important design consideration. This paper presents a novel...