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DELTA
2008
IEEE
13 years 11 months ago
AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis
Re-using embedded resources for implementing builtin self test mechanisms allows test cost reduction. In this paper we demonstrate how to implement costefficient built-in self tes...
M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre
VTS
1998
IEEE
97views Hardware» more  VTS 1998»
13 years 9 months ago
On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Mat...
CORR
2011
Springer
151views Education» more  CORR 2011»
12 years 12 months ago
A Simulation Experiment on a Built-In Self Test Equipped with Pseudorandom Test Pattern Generator and Multi-Input Shift Register
This paper investigates the impact of the changes of the characteristic polynomials and initial loadings, on behaviour of aliasing errors of parallel signature analyzer (Multi-Inp...
A. Ahmad
DATE
2003
IEEE
99views Hardware» more  DATE 2003»
13 years 10 months ago
RF-BIST: Loopback Spectral Signature Analysis
Built-In Self-Test (BIST) becomes important also for more complex structures like complete front-ends. In order to bring down the costs for the test overhead, Spectral Signature A...
Doris Lupea, Udo Pursche, Hans-Joachim Jentschel
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
13 years 9 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi