18 search results - page 1 / 4 » Abstraction of Graph Transformation Systems by Temporal Logi... |
VSTTE
2005
Springer
13 years 10 months ago
2005
Springer
CAV
2010
Springer
13 years 5 months ago
2010
Springer
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transforma...
FASE
1998
Springer
13 years 9 months ago
1998
Springer
A loose semantics for graph transformation rules which has been developed recently is used in this paper for the compositional verification of specifications. The main conceptual t...
TABLEAUX
1998
Springer
13 years 9 months ago
1998
Springer
ple (Extended Abstract) Edmund M. Clarke and Sergey Berezin Carnegie Mellon University -- USA Model checking is an automatic verification technique for finite state concurrent syst...
CC
2001
Springer
13 years 9 months ago
2001
Springer
Abstract. We present a method of specifying standard imperative program optimisations as a rewrite system. To achieve this we have extended the idea of matching sub-terms in expres...