Sciweavers

47 search results - page 9 / 10
» Accelerated costas array enumeration using FPGAs
Sort
View
DAC
2004
ACM
13 years 10 months ago
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...
Philip Brisk, Adam Kaplan, Majid Sarrafzadeh
SIGMOD
2009
ACM
157views Database» more  SIGMOD 2009»
14 years 5 months ago
FPGA: what's in it for a database?
While there seems to be a general agreement that next years' systems will include many processing cores, it is often overlooked that these systems will also include an increa...
Jens Teubner, René Müller
ARC
2009
Springer
188views Hardware» more  ARC 2009»
14 years 4 days ago
Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator
Abstract. Monte Carlo simulation is one of the most widely used techniques for computationally intensive simulations in mathematical analysis and modeling. A multivariate Gaussian ...
Chalermpol Saiprasert, Christos-Savvas Bouganis, G...
IPPS
2007
IEEE
13 years 11 months ago
Distributed IDS using Reconfigurable Hardware
With the rapid growth of computer networks and network infrastructures and increased dependency on the internet to carry out day-to-day activities, it is imperative that the compo...
Ashok Kumar Tummala, Parimal Patel
PVLDB
2008
126views more  PVLDB 2008»
13 years 4 months ago
Parallelizing query optimization
Many commercial RDBMSs employ cost-based query optimization exploiting dynamic programming (DP) to efficiently generate the optimal query execution plan. However, optimization tim...
Wook-Shin Han, Wooseong Kwak, Jinsoo Lee, Guy M. L...