13 search results - page 1 / 3 » Accelerating architectural exploration using canonical instr... |
ISPASS
2006
IEEE
13 years 10 months ago
2006
IEEE
Detailed microarchitectural simulators are not well suited for exploring large design spaces due to their excessive simulation times. We introduce AXCIS, a framework for fast and ...
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific accelerators used in conjunc...
HPCA
2004
IEEE
14 years 4 months ago
2004
IEEE
Design of wakeup-free issue queues is becoming desirable due to the increasing complexity associated with broadcast-based instruction wakeup. The effectiveness of most wakeup-free...
CASES
2005
ACM
13 years 6 months ago
2005
ACM
Instruction set customization accelerates the performance of applications by compressing the length of critical dependence paths and reducing the demands on processor resources. W...
CASES
2008
ACM
13 years 6 months ago
2008
ACM
While customizable processors aim at combining the flexibility of general purpose processors with the speed and power advantages of custom circuits, commercially available process...