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ECRTS
2008
IEEE
13 years 11 months ago
Cache-Aware Real-Time Scheduling on Multicore Platforms: Heuristics and a Case Study
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson
VLSID
2009
IEEE
177views VLSI» more  VLSID 2009»
14 years 5 months ago
Accelerating System-Level Design Tasks Using Commodity Graphics Hardware: A Case Study
Many system-level design tasks (e.g. timing analysis, hardware/software partitioning and design space exploration) involve computational kernels that are intractable (usually NP-ha...
Unmesh D. Bordoloi, Samarjit Chakraborty
RTAS
1998
IEEE
13 years 9 months ago
Managing Memory Requirements in the Synthesis of Real-Time Systems from Processing Graphs
In the past, environmental restrictions on size, weight, and power consumption have severely limited both the processing and storage capacity of embedded signal processing systems...
Steve Goddard, Kevin Jeffay
IPPS
1998
IEEE
13 years 9 months ago
Performance Analysis of Parallel Embedded Real Time Systems Based on Measurement and Visualization
This paper describes an approach to carry out performance analysis on systems which combine two major characteristics: real-time behaviour and parallel computational structure. It ...
Javier García, Jose Luis Díaz de Arr...
RTCSA
2005
IEEE
13 years 11 months ago
Using UML 2.0 for System Level Design of Real Time SoC Platforms for Stream Processing
While enabling fast implementation and reconfiguration of stream applications, programmable stream processors expose issues of incompatibility and lack of adoption in existing st...
Yongxin Zhu, Zhenxin Sun, Alexander Maxiaguine, We...