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» Accuracy management for mixed-mode digital VLSI simulation
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GLVLSI
2000
IEEE
109views VLSI» more  GLVLSI 2000»
13 years 9 months ago
Accuracy management for mixed-mode digital VLSI simulation
Gary L. Dare, Charles A. Zukowski
VLSID
2002
IEEE
138views VLSI» more  VLSID 2002»
14 years 5 months ago
A Framework for Design Space Exploration of Parameterized VLSI Systems
The paper presents two new approaches to multiobjective design space exploration for parametric VLSI systems. Both considerably reduce the number of simulations needed to determin...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
ICCD
1993
IEEE
111views Hardware» more  ICCD 1993»
13 years 9 months ago
Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
Michael A. Riepe, João P. Marques Silva, Ka...
ITC
1998
IEEE
120views Hardware» more  ITC 1998»
13 years 9 months ago
Test generation in VLSI circuits for crosstalk noise
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital c...
Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer
VLSID
2006
IEEE
134views VLSI» more  VLSID 2006»
14 years 5 months ago
ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective
This paper presents the power and performance analysis of a digital, direct sequence ultra-wideband (DS-UWB) receiver operating in the 3 to 4 GHz band. The signal to noise and dis...
Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran