-Conventionallyself-test hardware is added after synthesis is completed. For highly sequential circuits like controllersthis design method eitherleads to high hardware overheadsor ...
A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are...
Chaohuang Zeng, Nirmal R. Saxena, Edward J. McClus...
We describe a new synthesis procedure for designing asynchronous controllers from burst-mode specifications, a class of specifications allowing multiple input change fundamental m...
A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state si...
Mikael Kerttu, Per Lindgren, Mitchell A. Thornton,...
This paper discusses the design and implementation of finite state machines (FSM) with combinational circuits that are built primarily from RAM blocks. It suggests a novel state as...