5 search results - page 1 / 1 » Acyclic circuit partitioning for path delay fault emulation |
AICCSA
2005
IEEE
13 years 10 months ago
2005
IEEE
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
DAC
1994
ACM
13 years 9 months ago
1994
ACM
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
EAAI
2007
13 years 4 months ago
2007
This paper presents a swarm intelligence based approach to optimally partition combinational CMOS circuits for pseudoexhaustive testing. The partitioning algorithm ensures reducti...
FPGA
1998
ACM
13 years 9 months ago
1998
ACM
Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing archit...