4 search results - page 1 / 1 » Adaptive Spill-Receive for robust high-performance caching i... |
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
MICRO
2006
IEEE
13 years 11 months ago
2006
IEEE
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache c...
VLDB
1998
ACM
13 years 9 months ago
1998
ACM
We present a new client cache consistency algorithm for client caching database management systems. The algorithm, called Asynchronous Avoidance-based Cache Consistency (AACC), pr...
HPCA
2011
IEEE
12 years 8 months ago
2011
IEEE
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...