47 search results - page 10 / 10 » Adaptive prefetching for shared cache based chip multiproces... |
ASAP
2008
IEEE
13 years 11 months ago
2008
IEEE
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
ISCA
2010
IEEE
13 years 6 months ago
2010
IEEE
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...