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» Address Code Generation for Digital Signal Processors
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DAC
2001
ACM
14 years 5 months ago
Address Code Generation for Digital Signal Processors
Sathishkumar Udayanarayanan, Chaitali Chakrabarti
ASPDAC
2001
ACM
137views Hardware» more  ASPDAC 2001»
13 years 8 months ago
Optimized address assignment for DSPs with SIMD memory accesses
This paper deals with address assignment in code generation for digital signal processors (DSPs) with SIMD (single instruction multiple data) memory accesses. In these processors ...
Markus Lorenz, David Koffmann, Steven Bashford, Ra...
ICC
2009
IEEE
116views Communications» more  ICC 2009»
13 years 2 months ago
Efficient Implementation of Binary Sequence Generator for WiMAX and WRAN on Programmable Digital Signal Processor
In this paper, an efficient design for implementing binary sequence generator on 32-bit instruction execution mode TI TMS320C6416 DSP is presented. The main goal is to achieve high...
Lok Tiing Tie, Ser Wah Oh, K. J. M. Kua
HICSS
2000
IEEE
110views Biometrics» more  HICSS 2000»
13 years 9 months ago
Reverse Compilation for Digital Signal Processors: A Working Example
We describe the implementation and use of a reverse compiler from Analog Devices 21xx assembler source to ANSI-C with optional use of the language extensions for the TMS320C6x pr...
Adrian Johnstone, Elizabeth Scott, Tim Womack
CASES
2001
ACM
13 years 8 months ago
The very portable optimizer for digital signal processors
Although retargetability has been a major design concern for many compilers, retargetability is a vitally important issue for Digital Signal Processors(DSPs) because the architect...
Sungjoon Jung, Yunheung Paek