17 search results - page 1 / 4 » Address compression for scalable load store queue implementa... |
MICRO
2005
IEEE
13 years 10 months ago
2005
IEEE
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
IBMRD
2006
13 years 4 months ago
2006
Because they are based on large content-addressable memories, load-store queues (LSQ) present implementation challenges in superscalar processors, especially as issue width and nu...
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
ISLPED
2006
ACM
13 years 10 months ago
2006
ACM
Buffering more in-flight instructions in an out-of-order microprocessor is a straightforward and effective method to help tolerate the long latencies generally associated with ...