17 search results - page 4 / 4 » Address compression for scalable load store queue implementa... |
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
Traditional pulldown comparators that are used to implement associativeaddressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the co...
HPCA
2007
IEEE
14 years 5 months ago
2007
IEEE
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...