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» Address generation for memories containing multiple arrays
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ICCAD
2007
IEEE
92views Hardware» more  ICCAD 2007»
14 years 2 months ago
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays
Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we sug...
M. Haykel Ben Jamaa, Kirsten E. Moselund, David At...
SAC
2005
ACM
13 years 11 months ago
The container loading problem
This paper addresses single and multiple container loading problems. We propose to use dynamic prioritization to handle awkward box types. The box type with a higher priority will...
Andrew Lim, Xingwen Zhang
MIDDLEWARE
2010
Springer
13 years 4 months ago
Automatically Generating Symbolic Prefetches for Distributed Transactional Memories
Abstract. Developing efficient distributed applications while managing complexity can be challenging. Managing network latency is a key challenge for distributed applications. We ...
Alokika Dash, Brian Demsky
CGO
2008
IEEE
14 years 2 days ago
Automatic array inlining in java virtual machines
Array inlining expands the concepts of object inlining to arrays. Groups of objects and arrays that reference each other are placed consecutively in memory so that their relative ...
Christian Wimmer, Hanspeter Mössenböck
LCPC
2007
Springer
13 years 11 months ago
Multidimensional Blocking in UPC
Abstract. Partitioned Global Address Space (PGAS) languages offer an attractive, high-productivity programming model for programming large-scale parallel machines. PGAS languages, ...
Christopher Barton, Calin Cascaval, George Alm&aac...