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ICCAD 2007 International Conference on Computer-Aided Design

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ICCAD
2007
IEEE

281views Hardware» more ICCAD 2007»

Archer: a history-driven global routing algorithm

14 years 1 months ago

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Global routing is an important step in the physical design process. In this paper, we propose a new global routing algorithm Archer, which resolves some of the most common problem...

Muhammet Mustafa Ozdal, Martin D. F. Wong

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Id	Views	Title	Status

1	281	Archer: a history-driven global routing algorithm	claim
2	234	Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors	claim
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4	173	Bounding L2 gain system error generated by approximations of the nonlinear vector field	claim
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7	164	Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates	claim
8	164	Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques	claim
9	161	Clustering based pruning for statistical criticality computation under process variations	claim
10	160	Approximation algorithm for the temperature-aware scheduling problem	claim
11	158	Strategies for improving the parametric yield and profits of 3D ICs
12	157	Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture	claim
13	153	Checking equivalence of quantum circuits and states	claim
14	151	A design flow dedicated to multi-mode architectures for DSP applications	claim
15	148	Fast exact Toffoli network synthesis of reversible logic	claim
16	144	Voltage island-driven floorplanning	claim
17	143	TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction	claim
18	140	Thermal-aware Steiner routing for 3D stacked ICs	claim
19	139	Remote activation of ICs for piracy prevention and digital right management	claim
20	139	Using functional independence conditions to optimize the performance of latency-insensitive systems	claim
21	137	Combining static and dynamic defect-tolerance techniques for nanoscale memory systems	claim
22	137	Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding	claim
23	135	A selective pattern-compression scheme for power and test-data reduction	claim
24	134	Hybrid CEGAR: combining variable hiding and predicate abstraction	claim
25	134	Efficient decoupling capacitance budgeting considering operation and process variations	claim
26	132	Principle Hessian direction based parameter reduction with process variation	claim
27	131	Low-overhead design technique for calibration of maximum frequency at multiple operating points	claim
28	130	Modeling, optimization and control of rotary traveling-wave oscillator	claim
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32	128	Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs	claim
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34	124	3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits	claim
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38	119	IntSim: A CAD tool for optimization of multilevel interconnect networks	claim
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41	116	Device and architecture concurrent optimization for FPGA transient soft error rate	claim
42	115	Parameterized model order reduction via a two-directional Arnoldi process	claim
43	115	Timing optimization by restructuring long combinatorial paths	claim
44	113	Combinational and sequential mapping with priority cuts	claim
45	113	The FAST methodology for high-speed SoC/computer simulation	claim
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47	110	A hybrid scheme for compacting test responses with unknown values	claim
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50	108	Novel wire density driven full-chip routing for CMP variation control	claim
51	108	A frequency-domain technique for statistical timing analysis of clock meshes	claim
52	107	Computation of minimal counterexamples by using black box techniques and symbolic methods	claim
53	107	Formal verification at higher levels of abstraction	claim
54	106	A general model for performance optimization of sequential systems	claim
55	105	ECO timing optimization using spare cells	claim
56	105	High-performance routing at the nanometer scale	claim
57	105	Victim alignment in crosstalk aware timing analysis	claim
58	103	Enhancing design robustness with reliability-aware resynthesis and logic simulation	claim
59	102	Scalable exploration of functional dependency by interpolation and incremental SAT solving	claim
60	101	A novel SoC design methodology combining adaptive software and reconfigurable hardware	claim
61	101	Analog placement with common centroid constraints	claim
62	100	Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization	claim
63	100	Parallel domain decomposition for simulation of large-scale power grids	claim
64	99	Automating post-silicon debugging and repair	claim
65	99	Temperature aware microprocessor floorplanning considering application dependent power load	claim
66	98	Device-circuit co-optimization for mixed-mode circuit design via geometric programming	claim
67	98	Equalized interconnects for on-chip networks: modeling and optimization framework	claim
68	97	Gate sizing by Lagrangian relaxation revisited	claim
69	96	Monte-Carlo driven stochastic optimization framework for handling fabrication variability	claim
70	92	Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays	claim
71	91	Variation-aware task allocation and scheduling for MPSoC	claim
72	91	A fast band-matching technique for interconnect inductance modeling	claim
73	91	Sizing and placement of charge recycling transistors in MTCMOS circuits	claim
74	88	Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs	claim
75	87	Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design	claim
76	86	An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon	claim
77	86	Minimizing leakage power in sequential circuits by using mixed Vt flip-flops	claim
78	86	Stimulus generation for constrained random simulation	claim
79	83	Unified adaptivity optimization of clock and logic signals	claim
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82	67	Stabilizing schemes for piecewise-linear reduced order models via projection and weighting functions	claim
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84	64	An incremental learning framework for estimating signal controllability in unit-level verification	claim

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