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» Advanced tools for simulation and design of oscillators PLLs
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ASPDAC
2007
ACM
107views Hardware» more  ASPDAC 2007»
13 years 8 months ago
Advanced tools for simulation and design of oscillators/PLLs
We present a robust, automated oscillator macromodeling technique for extracting comprehensive phase and amplitude macromodels from oscillators' SPICE circuit descriptions. Th...
Xiaolue Lai, Jaijeet S. Roychowdhury
ICCD
2001
IEEE
88views Hardware» more  ICCD 2001»
14 years 1 months ago
Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective
CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper...
Payam Heydari, Massoud Pedram
GLVLSI
2005
IEEE
147views VLSI» more  GLVLSI 2005»
13 years 10 months ago
1-V 7-mW dual-band fast-locked frequency synthesizer
This paper presents a fully integrated 1-V, dual band, fastlocked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 ...
Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen
DAC
1996
ACM
13 years 8 months ago
Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools
This paper provides a case study that shows how a demanding application stresses the capabilities of today's CAD tools, especially in the integration of products from multipl...
Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vr...
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
13 years 10 months ago
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi,...