80 search results - page 1 / 16 » Algorithms for a switch module routing problem |
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
We consider a switch module routing problem for symmetric array FPGAs. The work is motivated by two applications. The rst is that of eciently evaluating switch module designs [8]...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
–An FPGA switch box is said to be hyper-universal if it is routable for all possible surrounding multi-pin net topologies satisfying the routing resource constraints. It is desir...
ITNG
2006
IEEE
13 years 10 months ago
2006
IEEE
—In this paper, we address the scheduling problem for Clos-network switches with no buffers at the central stage. Existing scheduling (dispatching) algorithms for this type of sw...
PACT
2005
Springer
13 years 10 months ago
2005
Springer
Abstract. The hotspot seriously degrades the performance of a parallel algorithm but there have not been many methods proposed for this problem. Without modification of mesh topolo...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
Several industrial FPGA routing architectures have been shown to have no efficient routing algorithms (unless P=NP) [3,4]. Here, we further investigate if the intractability of th...