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» Algorithms for a switch module routing problem
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SIGMETRICS
2011
ACM
182views Hardware» more  SIGMETRICS 2011»
12 years 8 months ago
Fine-grained latency and loss measurements in the presence of reordering
Modern trading and cluster applications require microsecond latencies and almost no losses in data centers. This paper introduces an algorithm called FineComb that can estimate ï¬...
Myungjin Lee, Sharon Goldberg, Ramana Rao Kompella...
INFOCOM
2006
IEEE
13 years 11 months ago
ISP and Egress Path Selection for Multihomed Networks
— Multihoming has been used by stub networks for several years as a form of redundancy, improving the availability of Internet access. More recently, Intelligent Route Control (I...
Amogh Dhamdhere, Constantinos Dovrolis
CCECE
2006
IEEE
13 years 11 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
13 years 10 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni
FPL
2010
Springer
124views Hardware» more  FPL 2010»
13 years 3 months ago
Finding System-Level Information and Analyzing Its Correlation to FPGA Placement
One of the more popular placement algorithms for Field Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement ...
Farnaz Gharibian, Lesley Shannon, Peter Jamieson