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» Allocating isolation levels to transactions
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HPCA
2007
IEEE
14 years 5 months ago
A Memory-Level Parallelism Aware Fetch Policy for SMT Processors
A thread executing on a simultaneous multithreading (SMT) processor that experiences a long-latency load will eventually stall while holding execution resources. Existing long-lat...
Stijn Eyerman, Lieven Eeckhout
SP
1999
IEEE
125views Security Privacy» more  SP 1999»
13 years 9 months ago
A Multi-Threading Architecture for Multilevel Secure Transaction Processing
A TCB and security kernel architecture for supporting multi-threaded, queue-driven transaction processing applications in a multilevel secure environment is presented. Our design ...
Haruna R. Isa, William R. Shockley, Cynthia E. Irv...
DATE
2009
IEEE
151views Hardware» more  DATE 2009»
14 years 1 days ago
Combined system synthesis and communication architecture exploration for MPSoCs
In this paper, a novel design space exploration approach is proposed that enables a concurrent optimization of the topology, the process binding, and the communication routing of ...
Martin Lukasiewycz, Martin Streubühr, Michael...
EDBT
2006
ACM
194views Database» more  EDBT 2006»
14 years 5 months ago
On Concurrency Control in Sliding Window Queries over Data Streams
Abstract. Data stream systems execute a dynamic workload of longrunning and one-time queries, with the streaming inputs typically bounded by sliding windows. For efficiency, window...
Lukasz Golab, Kumar Gaurav Bijay, M. Tamer Öz...
SIGMOD
1992
ACM
111views Database» more  SIGMOD 1992»
13 years 9 months ago
Performance Evaluation of Extended Storage Architectures for Transaction Processing
: The use of non-volatile semiconductor memory within an extended storage hierarchy promises significant performance improvements for transaction processing. Although page-addressa...
Erhard Rahm