27 search results - page 1 / 6 » An Approach to the Development of a IDDQ Testable Cell Libra... |
DFT
1994
IEEE
13 years 9 months ago
1994
IEEE
EURODAC
1990
IEEE
13 years 9 months ago
1990
IEEE
: In this paper logical cells and algorithms are presented supporting the design of pseudo-exhaustively testable circuits. The approach is based on real hardware segmentation, inst...
VLSID
1999
IEEE
13 years 9 months ago
1999
IEEE
To minimize the time to market and cost of new sub 0.25um process technologies and products, PDF Solutions, Inc., has developed a new comprehensive approach based on the use of pr...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
- This paper presents a methodology for concurrently optimizing an IC fabrication process and a standard cell library in order to maximize overall yield. The approach uses the Conc...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited ca...